Apply as ASIC Design Engineer 

Responsibilities:
Architectural design, RTL implementation in SystemVerilog, and constraining for ASIC technology
Integration of IP components and test infrastructure
Scripting to automate design-flow and test procedures
Close collaboration with design partners
Review of synthesis and back-end reports
Write design specifications and documentation
Development of lab test and hardware bring-up infrastructure

Qualifications:
A university degree in Electrical Engineering / Computer Engineering
Strong technical and theoretical background of digital VLSI design
3+ years of experience in digital design front-end flow (ASIC or FPGA), back-end flow as a plus
Good command of English with German skills as a plus

We offer
An exciting occupation with complex, technical challenges
A young and dynamic team with short lines of communication
A culture, welcoming high engagement and entrusting you with a broad range of duties
Excellent technical and personal development opportunities
Annual gross salary: starting from EUR 50.000, overpayment according to skills and experience